Seebeck/peltier thermoelectric conversion element with parallel nanowires of conductor or semiconductor material organized in rows and columns through an insulating body and process

ABSTRACT

A novel and effective structure of a stackable element (A 1 ,A 2 ) or more generally adapted to be associated modularly to other similar elements to form a septum of relatively large dimensions for a Seebeck/Peltier thermoelectric conversion device, may be fabricated with common planar processing techniques. The structure basically consists of a stack (A 1 , A 2 ) of alternated layers of a first dielectric material ( 2 ), adapted to be deposited in films of thickness lesser than or equal to about 50 nm, of low heat conductivity and which is etchable by a solution of a specific chemical compound, and of a second dielectric material ( 3 ) of low heat conductivity that is not etched by the solution. For the whole width, the stack is interrupted by parallel trenches (T 1 , T 2 , T 3 ) the width (w) of which may correspond to the minimum linewidth of definition allowed by the resolution of the lithographic process used for defining the parallel trenches, but which may eventually be limited by other parameters, in primis the height of the stack (h) to be subjected to the vertical etch to cut the stack in order to form the parallel trenches.

BACKGROUND

1. Field of the Invention

The present disclosure relates in general to Seebeck/Peltierthermoelectric conversion devices and in particular to devices utilizingparallel nanowires of conductor or semiconductor material extendingacross an insulating septum.

2. General Notions

The Seebeck effect is a thermoelectric phenomenon whereby in elongatedconductors or semiconductors, a temperature difference between portionsthereof generates electricity. The effect, discovered by the physicistThomas J. Seebeck in 1821, manifests itself as a difference in potentialbetween the ends of a metal bar subjected to a temperature gradient ∇T.In a circuit including two junctions between two materials A and B attemperatures T₁ and T₂, the resulting voltage is given by:

$\begin{matrix}{V = {\int_{T_{1}}^{T_{2}}{\left\lbrack {{S_{B}(T)} - {S_{A}(T)}} \right\rbrack \ {T}}}} & (1)\end{matrix}$

wherein: S_(A) and S_(B) are the Seebeck coefficients (also calledthermoelectric power) related to two materials A and B. The voltagevalues are typically in the order of several μV/K. The Seebeckcoefficient depends from the material, from absolute temperature andfrom morphological characteristics. The Seebeck effect can be exploitedfor measuring temperature in terms of voltage differences generated in acircuit comprising a junction of different materials (thermocouple) orfor generating electrical energy by connecting in series a plurality ofthermocouples (thermopile).

From a microscopic point of view, the charge carriers (electrons inmetals, electrons and holes in semiconductors, ions in ionic conductors)will diffuse when one end of an elongated conductor is at a differenttemperature of the other end. The hotter carriers will diffuse towardsthe portion at lower temperature as far as causing different carrierdensities in the cooler and hotter portions of the conductor. In aninsulated system, equilibrium will be reached when by diffusion, heatwill become uniformly distributed along the whole conductor.Re-distribution of thermal energy due to the motion of charge carriers(thermal current) is obviously associated to an electric current whichwill nullify itself when the conductor temperature becomes uniform.

In a system wherein two junctions connected in a circuit are kept at aconstant temperature difference, the thermal current will be constanttoo and therefore there will be a continuous flow of charge carriers inthe circuit.

Mobility of the carriers is reduced by scattering phenomena atimpurities, grain boundaries and similar defects present in theconducting material and by lattice vibrations (phonons). Therefore, theSeebeck effect is strongly dependent from density of impurities andcrystallographic defects and from the phonon spectrum of the material.

Phonons move along the thermal gradient loosing energy by interactingwith electrons or other carriers and with lattice imperfections. It isuseful to define a thermoelectric factor of merit of a material as:Z=S²σ/κ, where κ and σ are the thermal and electrical conductivities ofthe material, respectively.

From the technological point of view, the use of generators based uponthe Seebeck effect is considered potentially interesting. More than halfthe heat produced in a thermal plant is usually dissipated as lowenthalpy heat, it is estimated that about 15 millions of megawatts arewasted in the energy conversion processes. Availability of Seebeckgenerators, able to convert even only partially such a waste heat inelectricity would be able to impact positively on the energy problem.

However, thermoelectric generators have an extremely low efficiency. Forexample, in case of a thin film of n silicon, doped with 5×10¹⁵ As atomsper cm², the factor of merit, at room temperature, would be Z≈3×10⁻⁵K⁻¹; whereas values of ZT≈1 can be obtained only with costly materialsof limited availability such as Bi₂Te₃, Sb, Se and alloys thereof.

Practically, apart from some uses of high added value such asthermoelectric generation in space crafts, thermoelectric generatorsmade with massive amounts of low cost materials of ample availabilitywould achieve conversion yields of just about 7%. By comparison aturbine engine is able to convert about 20% of thermal energy in usefulelectrical current.

Recently it has been demonstrated [1, 2] that with a system based on anextremely slender conductor in the form of a silicon nanowire of about20 nm and rugged outer surface, a high thermoelectric figure of meritcan be achieved. The increased Z figure of the material derives from adecoupling of the free average paths of phonons and electrons caused bya different incidence of scattering at the surface of the two species.In particular, the important contribution to heat conductivity ofacoustic phonons of lower frequency (of larger wavelength) is eliminatedbecause the density of phonons of wavelength larger than the crosssectional size of the wire practically becomes null. Consequently, theheat conductivity of silicon drops from ≈150 W m⁻¹K⁻¹ (at roomtemperature for massive Si) to ≈1.6 Wm⁻¹K⁻¹ (at room temperature for 20nm Si nanowires), whilst by contrast the electrical conductivity doesnot suffers an equivalent drastic decrement.

Formation of test nanowires of a suitable conductor or semiconductormaterial has for a long time been possible only with laboratorytechniques hardly suited for fabricating thermo-electric conversionelements of commercially viable structure and size which could beassociated for realizing septa of thermoelectric conversion, capable offunctioning at commercially significative power levels and which couldbe industrially fabricated on a mass production scale.

A method of fabricating nanowires of elements of the IV Group of thePeriodic Table or alloy thereof, without requiring advanced lithographictechniques, and including treatment steps for enhancing surfaceruggedness, is disclosed in prior Italian patent application of one sameapplicant, filed on Apr. 11, 2008, published as WO 2009/12531. Themethod contemplates optional ion implantation and a thermo-cycling ofthe nanowires to induce creation of voids in the bulk of the material inorder to usefully modify in a significantly different manner the meanfree paths of phonons and electrons.

The prior application discloses the way a single level array of parallelnanowires and resultant structure may be fabricated in an industriallyscalable manner, to be eventually stacked with similar single levelarray structures in order to incrementally increase the size of theopposite surfaces, respectively hot and cold, of a septum ofthermoelectric conversion, reduce internal electrical resistance andincrease the power that can be yielded from the device.

The formation of a single level array of parallel nanowires on thesurface of an insulating substrate by photolithographic definition,deposition of a conformal layer of conductor or semiconductor materialand successive anisotropic etch of the conformal layer, requires thefabrication of innumerable of such “monolayer” elements, each through arepetition of the same sequence of photolithographic definition,deposition and etch, which makes the process relatively costly andlimits the numerosity of nanowires that can be packed per unit of areaof thermal input/output of a practical conversion device thusconstituted.

OBJECTIVES AND SUMMARY OF THE INVENTION

A first objective of the inventors/applicants is to provide a structuralelement adapted to be modularly associated to other similar structuralelements, having a dense population of nanowires of a conductor or asemiconductor material organized in a plurality of rows and columns ofparallel nanowires supported on a single substrate achieving anoutstandingly great numerosity of nanowires per unit of area of theelement.

Another objective is to provide an efficient fabrication process adaptedto be conducted with common practices of planar processing technologyand having a relatively simple and low cost process flow.

Another objective is to provide a septum for a Seebeck/Peltierthermoelectric conversion device of dimensions suitable for powerapplications, composed by an unlimited number of structural elementsmodularly associated, each having a plurality of rows and columns ofparallel nanowires on a single substrate, with distinct metallizationsof connection in parallel of groups of nanowires, of a certainfractional number of the whole population of nanowires, over oppositesurfaces, respectively cold and hot, of the septum and metal lines orwires of connection in series of the groups of nanowires in parallel, totwo terminals of the device.

These objectives are achieved by a novel and effective structure of astackable element or more generally adapted to be associated modularlyto other similar elements to form a septum of relatively largedimensions for a Seebeck/Peltier thermoelectric conversion device,fabricable with common planar processing techniques.

The structure basically consists of a stack of alternated layers of afirst dielectric material, adapted to be deposited in films of thicknesslesser than or equal to about 50 nm, of low heat conductivity and whichis etchable by a solution of a specific chemical compound, and of asecond dielectric material of low heat conductivity that is not etchedby the solution.

For the whole width, the stack is interrupted by parallel trenches thewidth of which may correspond to the minimum linewidth of definitionallowed by the resolution of the lithographic process used for definingthe parallel trenches, but which may eventually be limited by otherparameters, in primis the height of the stack to be subjected to thevertical etch to cut the stack in order to form the parallel trenches.

These trenches, produced by transversally cutting the stack, have overthe opposite etch surfaces parallel cavities of “retreat” of therespective etch front of the first dielectric material by the dissolvingaction of the etching solution, for an average in-depth of the etchingsgenerally comprised between about 15 and about 35 nm.

Nanowire-like residues of a conformally deposited sacrificial layer ofconducting or semiconducting material of filling of the parallelcavities present on the opposite surfaces of the trenches, subsequentlyremoved from substantially planar vertical and horizontal surfaces,constitute as many parallel nanowires generally of non uniform crosssectional area and highly irregular surfaces of a conductor orsemiconductor filler material, organized in rows and columns across theslotted stack of alternated layers of different dielectric materials.

Therefore, though the element can be replicably fabricated in planartechnology, it comprises a two-dimension array of parallel nanowires,electrically insulated from one another, that extend from one side tothe other side of the stack, organized in rows of spaced parallelnanowires laying on a same level plane and columns of nanowires,extending orthogonally to the level planes.

Numerosity of alternated layers of different dielectric materials of thestack over the surface of an insulating substrate is theoreticallyillimited and is practically limited only by the ability of makingtrenches with substantially vertical sidewalls in a stack of alternatedlayers of different dielectric material, up to a limit height of thestack which may reach several tens of microns (μm), in other words, thelimit depth of slots that can be made with an acceptable geometry of thecross section of the parallel slots cut in the stack.

According to another aspect of the present disclosure, the novelfabrication process of a stackable element adapted to form a septum fora Seebeck/Peltier thermoelectric conversion device, comprises the stepsof:

-   a) depositing a first layer of one or the other of a first    dielectric material etchable by a solution of a chemical compound    and depositable in film of thickness lesser of or equal to 50 nm and    of a second dielectric material of low heat conductivity resistant    to said etching solution, on a flat substrate of a dielectric    material of low heat conductivity resistant to said etching    solution;-   b) depositing over said first layer of one of the two different    dielectric materials a layer of the other dielectric material and    repeating steps a) and b) for a number of times sufficient to reach    a desired height of the stack of layers (a) alternated to layers b);-   c) forming or applying a mask over the stack defining parallel etch    lines of width equivalent to the minimum linewidth definable with    the lithographic technique used, extending for the whole width of    the stack and spaced by one or more micrometers (μm);-   d) etching by sputtering, reactive plasma, or plasma through the    opening of the mask the multilayer stack forming parallel trenches    as deep as exposing the surface of the substrate;-   e) etching with said solution the opposite etch surfaces of said    etchable first dielectric material of thickness (generally not    greater than about 50 nm) as far as retreat the etch surfaces    between the adjacent layers of the second dielectric material (not    etched by the solution), for an average distance of about 20 nm,    forming parallel nanocavities over the opposite etch surfaces along    each trench;-   f) after having eliminated eventual residues of the mask, depositing    under conditions of high conformity to the receiving surfaces a    layer of conductor or semiconductor material having a relatively    high intrinsic Seebeck coefficient, filling at least partially said    parallel cavities as far as growing over vertical and horizontal    planar surfaces a sacrificial conformal layer free of    discontinuities;-   g) forming anew or applying again said mask over the stack;-   h) etching through the mask openings by sputtering, reactive plasma    or plasma the conformally deposited sacrificial layer of conductive    or semiconducting material as far as completely removing it from    vertical and horizontal surfaces, leaving residual nanowires of the    conductor or semiconductor filler inside said parallel cavities.

The invention is defined in the annexed claims.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows the architecture of a septum for a Seebeck/Peltierthermoelectric conversion device composed of elements of the presentdisclosure, stacked and bonded together.

The series from FIG. 2 to FIG. 6 illustrates with schematical crosssectional view of structural features of the element, fundamental stepsof the fabrication process of the present disclosure;

FIG. 7 and FIG. 8 show few possible transversal cross sectional sampleviews of residues of the filler of the nanocavities that constitute thesingle nanowires of conductor or semiconductor material of themultilevel structure of the element of the present disclosure.

Exemplary Embodiments of the Invention

Embodiments of the claimed invention will now be described for purelyillustrative purpose making reference to the attached drawings.

Numerosities and organization of the elements and electrical connectionsof the device, as well as the material used and related processingconditions may be differently set and chosen by the designer based onpreferences and/or specific requirements of the application. Therefore,the invention is not intended to be limited to the exemplary embodimentsherewith described and illustrated.

FIG. 1 shows the basic architecture of a septum for a Seebeck/Peltierthermoelectric conversion device, composed of elements of the presentdisclosure stacked and bonded together. The illustrated fragment is oftwo adjacent elements, A1 and A2, respectively, each composed of a flatsubstrate 1 of a dielectric material of low heat conductivity, resistantto the etching solutions and temperatures contemplated by thefabrication process of the element and to the temperatures of operationof the thermoelectric conversion device. Suitable substrate materialsare thin sheets of glass, glass-ceramic, ceramic, sintered materials orcer-met of alumina, refractory oxides of metals of Groups IV B and V Bof the Periodic Table of elements, mixed oxides and mixtures thereof,thermosetting resins, agglomerates and composites using epoxidic orphenolic binders and particles and/or fibers of nonconducting materials.

Over the substrate 1 there is a stack composed of layers of a firstdielectric material 2 deposited in a film of thickness lesser than orequal to about 50 nm and etchable with a solution of a suitable chemicalcompound, alternated to layers 3 of a second dielectric material of lowheat conductivity which is not etched by the solution.

The first dielectric material deposited in films 2 of thickness lesserthan or equal to 50 nm, may be an oxide, for example SiO₂ or otherdielectric oxide that can be deposited in highly conformal ultrathinfilms.

The second dielectric material 3 may be a nitride, for example Si₃N₄ ora refractory oxide, mixed oxide or other dielectric compound that issubstantially not etched or in any case only lightly attacked by theetching solution of the first dielectric material.

The stack has parallel slots across the whole width W of the stackforming parallel trenches T1, T2, T3, . . . , extending along the wholewidth of the substrate 1. The width w of the trenches may correspond tothe minimum linewidth that can be practically defined with thelithographic technique used and, by sing common photolithography, maygenerally be comprised between 150 nm and 1 μm, while the separationbetween adjacent trenches, corresponding to the width or thickness ofthe parallel walls or slices of multilayered stack that remains afterproducing the trenches, is the lesser possible compatibly withpreservation of sufficient mechanical stability of the slender parallelwalls during the steps of cutting the stack for creating the paralleltrenches of wet etching of the etchable layers, of depositing a fillerlayer of conducting or semiconducting material and of removing thedeposited material from planar surfaces.

The stack may reach the height h theoretically illimited, being possibleto increment the number of overlaid layers 2 and 3 and in practice islimited by the technological ability of producing parallel cuts ofminimum width w and periodicity (pitch) through the whole thickness W ofthe stack, in order to maximize the density of nanowires per unit area,compatibly with the requirement of ensuring sufficient mechanicalstability to the residual walls of stack between adjacent trenchesduring the etching step, a selective isotropic wet etching of one of thetwo different dielectrics and subsequent step of filling the cavitiesand of removing the filler material from the planar surfaces of thestructure.

By creating the parallel slots by anisotropic etch by sputtering,reactive plasma or plasma etching of the dielectric materials of thealternated layers 2 and 3 of the stack, using a definition mask ofcommon photoresist, it is possible to perform cuts with substantiallyparallel (vertical) etch surface through thicknesses of the stack(height h) from several tens of μm as far as to few millimeters.

Of course, the greater is the height h of the stack, the greater willneed to be the periodicity or pitch of replication of the paralleltrenches, that is of the thickness of the residual parallel wallsseparating adjacent trenches. Normally, the height of the stack h andthe periodicity (pitch) may be of the same order of magnitude.

Relative resistance to attack by a specific chemical solution of thedielectric material of the layers 3 compared to the dielectric materialof layers 2 which dissolves at a certain rate in the solution, permitsthe formation of nanodimensioned parallel cavities along the exposedetch surfaces of each trench T1, T2, T3, . . . , Ti, . . . , because ofa progressing retreat of the respective etch front of the dielectricmaterial of the thin layer 2 from the plane of the etch surface of thetrench. Inside these parallel cavities remain nanowire like residues ofa conductor or semiconductor filler material of a conformally depositedsacrificial layer filling the parallel nanocavities and which issubsequently removed by anisotropic etching from the substantiallyplanar etch surfaces of the trenches. Such residues 4 constituteparallel nanowires of the filler material, perfectly organized in rowsand columns.

The filler material constituting the residual nanowires 4 may be asemiconductor such as silicon with natural isotopic presence or with anenriched presence of ²⁹Si, intrinsic or doped with donor and/or acceptoratoms, a silicon-germanium alloy, eventually isotopically enriched with²⁹Si, intrinsic or doped with donor and/or acceptor atoms and equivalentsemiconductor materials, a metal such as tungsten, titanium or alloysthereof, a metal alloy of semi-metals, an alloy between a metal and asemi-metal. The filler material may in any case be deposited in asubstantially conformal manner, adapted to fill parallel nanocavities asthose created in the opposite wall surfaces of each trench.

As shown in FIG. 1, elements thus constituted may be associatedmodularly together, for example by stacking one on the other and theparallel trench cavities of each element or of a complete septumconstituted by joining together several elements, are filled with adielectric material of extremely low heat conductivity such as forexample an aerogel of silica or alumina or of other refractory oxide,adapted to contribute to constitute a thermally insulating septum havingan overall (compounded) heat transmission coefficient as low aspossible.

To this end, definition of the parallel trenches T1, T2, T3, of thesingle elements is designed in order to determine a fill/void ratio aslow as possibly, compatibly with maintaining a sufficient mechanicalstability of the residual parallel walls of multilayered stack, thethickness of which may be the minimum capable of ensuring, besideselectrical separation between the nanowire on one side and the nanowireon the other side of the wall (at any level of the stack), also anadequate mechanical stability during the etching of the parallel cuts inthe stack as well as during the removal of the conformally depositedconductor or semiconductor filler material of the nanocavities formed inthe opposite surfaces of each trench.

This mechanical integrity requirement and insulating characteristics ofthe septum must not on the other end penalize beyond measuremaximization of the number of nanowires per unit area of oppositesurfaces of the septum at which terminate the opposite ends of all theparallel nanowires, in order to provide for an adequate cross section ofelectrical current conduction for limiting the internal resistance ofthe thermoelectric converter.

The architecture of the elements of the present disclosure and of athermoelectric conversion septum of relative large size composable witha plurality of elements, has no particular criticalness. The defectivitythat may be represented by single interrupted nanowires (in astochastically determined percentage) therefore not functioning, remainsof relatively little significance by virtue of the vast number ofnanowires that are eventually grouped together by connecting themelectrically in parallel with surface metallization islands over theopposite sides of the septum.

Irregularity of retreat of the etch surface of the thin dielectriclayers 2, typical of a wet chemical etching by contact with a solution(e.g. by immersion in the each solution) and irregularity of filling ofthe parallel nanocavities concur to the result that the residualnanowires 4 of conductor or semiconductor filler material generally havea varying cross section along their length, each single nanowire, thatis markedly varying in size and in terms of perimetral profile, asschematically depicted in the detail of FIG. 7. Moreover, within eachnanowire are frequently present inner voids and/or cracks, asschematically depicted in the detail of FIG. 8. All these irregularitiesenhance surface scattering phenomena of phonons along their propagationin the direction of heat transfer across the composite septum.

These advantageous characteristics of the parallel nanowires 4 of theelement of the present disclosure produce a remarkable increase of theSeebeck coefficient compared to nanowires of the same filler material,substantially compact, having a relatively uniform cross section and arelatively smooth surface, like those made according to the techniquedescribed in the above-identified prior patent application.

After having completed the stack and formed the residual nanowires, thetrench voids may be completely filled with a material having anextremely low heat transmission coefficient, for example an aerogel ofsilica or other insulating material, in order to consolidate themechanical stability of the so formed nanostructures and making theelements more easily handled when assembling (stacking) them togetherfor forming a septum of the desired size.

Alternatively, the association/stacking of the fabricated elements maytake place before proceeding to fill the trench voids of the compositearticle (septum) with the insulating material (aerogel).

As schematically depicted in FIG. 1, metallization strips 5 may bedefined over opposite surfaces of the septum at which terminate the endsof every single nanowire 4, in order to connect electrically in parallelper groups the nanowires 4, as depicted in the figure.

Constitution of a device of thermoelectric conversion by Seebeck/Peltiereffect, is completed by realizing electrical connections 6 among thedefined metallization islands over the opposite surfaces of thermalinput/output of the septum, in order to connect electrically in seriesthe groups of nanowires 4 in parallel, to two terminals of the wholeseries/parallel network of nanowires 4 of the septum.

These metallizations on opposite surfaces of a composite septum made bya plurality of elements may be defined by low cost print techniques(e.g. by serigraphy or ink jet printing) for defining the desiredpatterns of the metallic layer. Alternatively, the opposite surfaces ofeach element fabricated with techniques of planar fabrication processingmay be already coated with a common metal layer deposited, after havingsuitably slanted the opposite surfaces to be metallized of the elementto be no longer vertical but inclined, by carrying out a succession ofselective etchings of the two different dielectric materials. The etchsteps may be repeated, each for a preestablished interval of time,enhancing a first and a second chemical compound, for successivelyetching the different dielectrics. Thereafter, it will be possible toplanarly deposit and eventually photolithographically define a metallayer.

Elements thus made, for example with all the nanowires of the elementpre-connected electrically in parallel by an unpatterned metal layerdeposited on the opposite surfaces of the stack, with contact resistanceeffectively minimized because of the increased contact area with theends of the single nanowires due to the slanting of the end surfacescarried out through sequential etchings of the dielectrics on theopposite surfaces prior to depositing the metal layer, as well asbecause of the refined metallization techniques of modern planarfabrication processing, may be joined together to form blocks of acertain number of elements, all nanowires of which are preconnected inparallel and eventually connectable according to a desiredseries-parallel scheme, by a further metal layer (which may be of adifferent metal, for example a low melting alloy, applied by dipping thesurface of the septum in the molten alloy) formed over thepre-metallized surfaces of the planarly fabricated elements. Such ametal overlayer may than be defined according to a desiredseries-parallel electrical connection scheme of the whole population ofnanowires of a septum thus constituted.

The numerosity of nanowires per unit area of thermal input/output of theseptum of the present disclosure is at least three orders of magnitudegreater than that obtainable in a septum according to the closest priorart disclosed in the cited prior patent application published also as WO2009/1255317-A2. The maximum numerosity in a septum of the priortechnique is of 5×10⁶ cm⁻², whilst in a septum according to the presentdisclosure, it may reach 1.5×10¹⁰ cm⁻².

The element of the present disclosure can be fabricated in aparticularly efficient manner in terms of relative simplicity of theprocess flow, substantial absence of criticalnesses and low cost, with aprocess, an embodiment of which will now be described making referenceto the series of drawings from FIG. 2 to FIG. 6, which showschematically an enlarged detail (dimensionally not in scale) of a crosssection of the element being fabricated, in correspondence of one of themany parallel trenches.

With reference to FIG. 2, the fabrication process and in particular thestep of forming the multilayered stack of alternated layers 3, 2, 3, 2,. . . , of different dielectric materials, resistant to and etched,respectively, by a specific etching solution, over a substrate, forexample a thin sheet of a glass-ceramic material 1, may be efficientlycarried out in an apparatus of chemical deposition from vapor phase,suitably equipped and able to permit the performance of a succession ofdeposition steps of alternated dielectric layers of different materialwithin the same reactor, by modifying every time the conditions ofdeposition and the gaseous precursors introduced in the reactor.

Referring to the exemplary case depicted in the series of figures, thefirst layer deposited over the surface of the substrate 1 may be a layerof silicon nitride 3 of average thickness of about 40 nm or of about 100nm or more, depending on the fact that it be the material to be etchedor the material resistant to etching.

Conditions of deposition of silicon nitride (in the example the layers3) may contemplate:

-   -   deposition temperature of about 790° C.±200° C.    -   pressure of about 170 mTorr±100 mTorr    -   atmosphere: di-chlorosilane or other chlorosilanes or mixtures        thereof in presence of nitrogen and/or ammonia.

Having further established the time of deposition for obtaining thedesired thickness of silicon nitride of the layers 3, the atmosphere andthe deposition conditions are changed, carrying out common fluxing stepsand subsequent constitution of the correct atmosphere for carrying outthe deposition of the successive layer of a different dielectricmaterial 2, for example of silicon oxide and carrying out the depositionof the layer 2 at conditions that may be:

-   -   deposition temperature of about 950° C.±150° C.    -   pressure of about 200 Torr±150 Torr    -   atmosphere: di-chlorosilane and oxygen, optionally in presence        of water or nitrogen as diluent.

Once the preestablished deposition time for obtaining the desiredthickness of the layer 2 of silicon oxide, of about 40 nm or of about100 nm or more of thickness, depending on the fact that it be thematerial to be etched or the material resistant to etching, has elapsed,within the reactor are again re-established the conditions of depositionof the nitride for depositing a successive layer of silicon nitride overthe layer of silicon oxide and so forth growing a stack of alternatedlayers of silicon nitride 3 and of silicon oxide 2 for a height of thestack that may reach up to several millimeters.

With reference to FIG. 3, through a common photolithographic mask ofdefinition of parallel trenches Ti, the alternated layers of siliconnitride and silicon oxide are anisotropically etched by plasma, reactiveplasma or sputtering, as far as completely “slicing” the stack, exposingthe surface of the substrate 1 at the bottom of each trench. Generally,the etching may be conducted with any of the commonly used techniquesemployed in planar processing of multilayered stacks.

After having made the parallel slots across the stack of alternatedlayers of silicon nitride and silicon oxide on the substrate 1, thedielectric material of the layers 2 (in the example of silicon oxide) issubjected to isotropic wet etching in an aqueous solution ofhydrofluoric acid, progressively causing by dissolution of the oxide, aretreat of the etch surface of the layers 2 from the plane of theopposite surfaces of definition of the trenches Ti, as depictedschematically in FIG. 4.

Of course, as will be evident to the reader knowledgeable of siliconprocessing techniques, in the specific exemplary embodiment ofalternated layers of silicon oxide and of silicon nitride, thedielectric material that is etchable with a specific solution forprogressively retreat the etched surface may alternatively be thesilicon nitride, using in this case as selective etching solution of thenitride in respect to the oxide, a phosphoric acid melt (H₃PO₄) or,alternatively a hot aqueous solution of phosphoric acid.

After having removed residues of the definition mask of the paralleltrenches, rinsed and dried the article of manufacture, a sacrificiallayer 4 c of a conductor or semiconductor material 4 c is conformallydeposited such to fill the nanometric cavities produced over theopposite surfaces of the trenches by the retreat of the layers 2 ofdielectric material deposited with an average thickness of about 40 nmand successively etched between the dielectric layers 3 unaffected bythe etching solution, which may have a layer average thickness, forexample of about 100 nm.

This deposition step of the sacrificial conformally deposited layer ofmaterial thermo-electrically active is schematically depicted in FIG. 5.

In the exemplary embodiment, the deposited thermo-electrically activematerial may be silicon deposited under conditions of high conformityfor example, at the following deposition conditions:

-   -   temperature of about 610° C.±200° C.    -   pressure of about 170 mTorr    -   atmosphere: silane, optionally in presence of chlorosilanes and        H₂ or N₂ as diluent.

With reference to FIG. 2, the sacrificial filler layer 4 c is subjectedto unmasked anisotropic etching for example by reactive ion etching(RIE) as far as completely removing the deposited material of theconformally deposited layer 4 c from the horizontal and vertical planarsurfaces leaving residues of the filler material within the nanocavitiespurposely produced on the opposite surfaces of the parallel trenches Ti.These residues of filler material constitute as many nanowires 4parallel to each other, electrically insulated from one another,organized in rows (on level planes of the stack) and in columns, as maybe observed in FIG. 6.

The nanowires 4 extend from one side to the other of the trench.

The conditions of formation of the nanocavities by selective isotropicetching of one of the two different dielectric materials used forforming the stack of alternate layers, as well as the conditions offilling of the parallel nanocavities by the conformally depositedthermo-electrically active material, are processes, the progression andcompletion of which are intrinsically irregular, being in the first caseaffected by crystallographic and morphological differences of thedeposited dielectric material of the layers being etched and in thesecond case affected by similar irregularities of retreat of the etchfront of the dielectric material being selectively etched isotropicallyby contact with an etching solution or melt.

The combined result of these factors is such to determine the formationof wire like residues of the material of the conformally depositedsacrificial layer with a disuniform cross section along the extension ofthe single nanowire, that is of varying dimensions and perimetralprofile, as well as an outer surface morphologically rugged andirregular, as schematically depicted in the detail of FIG. 7.

Moreover, the filling process by the thermo-electrically activematerial, though deposited under conditions of high conformity to thereceiving surface morphology, progresses in a way that leads to theformation of cracks and inner voids (because of edge effects), asschematically depicted in the detail of FIG. 8.

These intrinsic morphological and geometrical characteristics of thenanowires left inside the nanocavities strongly favor surface scatteringof phonons. This is compounded in a sensible increase of the observedSeebeck coefficient compared to differently fabricated nanowires of thesame material but with a diameter or with cross sectional dimensionsrelatively constant, substantially compact and having a relativelysmooth outer surface.

BIBLIOGRAPHY

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1. An element (A1, A2) fabricable with planar processing techniques,modularly associable to other similar elements for constituting a septumfor a Seebeck/Peltier thermo-electric conversion device, comprising astack of width (W) corresponding to the thickness of the septum and alength (L) corresponding to a dimension or fraction of a dimension ofthe surface area of the septum, the element having a population ofnanowires (4) of conductor or semiconductor material of high Seebeckcoefficient, parallel and insulated from one another extending acrossthe width (W) of the stack, organized in rows and columns, said stackcomprising: a) alternated layers of a first dielectric material (2)depositable in continuous film of thickness lesser than or equal to 50nm, etchable by a solution of a specific chemical compound, and of asecond dielectric material (3) of low heat conductivity not etchable bysaid solution; b) parallel trenches (T1, T2, T3, . . . , Ti . . . ) thelower limit of width (w) of which corresponds to the minimum linewidthof lithographic definition, spaced by at least 1 μm; c) parallelcavities (4 c) of retreat of the etch front of the layers of said firstdielectric material (2) by said etching solution, along oppositesurfaces of each trench; d) wirelike nanodimensioned residues of aconductor or semiconductor filler material of said parallel nanocavities(4 c) constituting said parallel spaced nanowires (4) organized in rowsand columns.
 2. The element of claim 1, wherein said conductor orsemiconductor material of high Seebeck coefficient belongs to the groupcomposed by an intrinsic or doped semiconductor, a metal, a metal alloy,an alloy of semimetals, an alloy between a metal and a semimetal andmixtures thereof.
 3. The element of claim 2, wherein said conductor orsemiconductor material of high Seebeck coefficient belongs to the groupcomposed of monocrystalline or polycrystalline silicon with naturalisotopic presence or enhanced presence of ²⁹Si, intrinsic or doped withdonor and/or acceptor atoms, a silicon-germanium alloy with naturalisotopic presence or enhanced presence of ²⁹Si, either intrinsic ordoped with donor and/or acceptor atoms, tungsten, titanium and alloysthereof.
 4. The element of claim 1, wherein said first dielectricmaterial (2) is SiO₂ and said second dielectric material (3) is Si₃N₄.5. The element of claim 1, wherein said first dielectric material (2) isS₃N₄ and said second dielectric material (3) is SiO₂.
 6. The element ofclaim 1, comprising a substrate (1) of a low heat conductivitydielectric material resistant to the etching solution of said firstdielectric material (2).
 7. The element of claim 1, wherein saidnanowires (4) have disuniform cross section along their longitudinalextension and morphologically rugged outer surface.
 8. The element ofclaim 1, characterized in that the stack has a density of nanowires (4)of average cross section of about 40 nm×20 nm, per unit of area of sidesurfaces of heat input/output the stack up to 5×10¹⁰ nanowires/cm². 9.The element of claim 1, wherein the height (h) of the stack and theperiodicity or pitch of replication of said parallel trenches are of thesame order of magnitude.
 10. A fabrication process for an element (A1,A2) modularly associable to other elements for constituting a septum fora Seebek/Peltier thermo-electric conversion device, comprising the stepsof: a) depositing a first layer of one or the other of a firstdielectric material (2) depositable in continuous film of thicknesslesser than or equal to 50 nm, etchable by a solution of a specificchemical compound and of a second dielectric material (3) of low heatconductivity not etchable by said solution, on a flat substrate (1) of alow heat conductivity dielectric material resistant to said solution; b)depositing over said first layer of one of said two different dielectricmaterials, a layer of the other dielectric material and repeating stepsa) and b) for a number of times sufficient to reach a desired height ofthe stack of layers of step a) alternated to layers of step b); c)forming or applying a mask over a stack defining parallel etch openings,the minimum limit of width (w) of which corresponds to the minimumlinewidth of definition of the lithographic technique used, spaced by atleast 1 μm, extending for the whole width (W) of the stack; d) etchingin plasma or in reactive plasma or by sputtering through said maskopenings the multilayered stack forming parallel trenches (T1, T2, T3, .. . , Ti, . . . ) deep as far as reaching the surface of said substrate(1); e) etching with said solution the etch surfaces of the layers ofsaid first dielectric material (2) as far as backing them in, betweenadjacent layers of said second dielectric material (3), by an averagedistance of 20 nm, forming parallel cavities (4 c) on the opposite etchsurfaces of each trench (T1, T2, T3, . . . Ti, . . . ); f) eventuallyremoving from the surface of the stack residues of said mask, chemicallydepositing from vapor phase conductor or semiconductor material of highintrinsic Seebeck coefficient, filling said parallel cavities (4 c) asfar as growing a conformal layer (4 m) free of discontinuities overhorizontal and vertical parallel surfaces of the slotted stack; g)forming or applying anew said mask over the surface of the stack; h)etching in plasma, in a reactive plasma or by sputtering through themask openings the conductor or semiconductor material of saidconformally deposited layer (4 m) as far as removing it completely fromsaid horizontal and vertical planar surfaces, leaving nanowire-likeresidues (4) of said conductor or semiconductor material inside saidparallel cavities (4 c).
 11. The process of claim 10, wherein saidconductor or semiconductor material of high intrinsic Seebeckcoefficient belongs to the group composed of a semiconductor intrinsicor doped, a metal, a metal alloy, an alloy between semi-metals, an alloybetween a metal and semimetal and mixtures thereof.
 12. The process ofclaim 11, wherein said conductor or semiconductor material of highintrinsic Seebeck coefficient belongs to the groups composed ofmonocrystalline or polycrystalline silicon with natural isotopicpresence or enhanced presence of ²⁹Si, intrinsic or doped with donorand/or acceptor atoms, a silicon-germanium alloy with natural isotopicpresence or enhanced presence of ²⁹Si, either intrinsic or doped withdonor and/or acceptor atoms, tungsten, titanium and alloys thereof. 13.The process of claim 10, wherein said first dielectric material (2) isSiO₂, said second dielectric material (3) is Si₃N₄ and said etchingsolution is an aqueous solution of hydrofluoric acid.
 14. The process ofclaim 10, wherein said first dielectric material (2) is Si₃N₄, saidsecond dielectric material (3) is SiO₂ and said etching solution is anaqueous solution or a melt of phosphoric acid.
 15. A septum for aSeebeck/Peltier thermo-electric conversion device composed of any numberof associable elements (A1, A2, . . . ), each comprising a stack ofwidth (W) corresponding to the thickness of the septum and a length (L)corresponding to a dimension or fraction of a dimension of the surfacearea of the septum, each element (A1, A2, . . . ) having a population ofnanowires (4) of conductor or semiconductor material of high intrinsicSeebeck coefficient, parallel and insulated from one another extendingacross the width (W) of the stack, organized in rows and columns, thestack of each element comprising: a) alternated layers of a firstdielectric material (2) depositable in continuous film of thicknesslesser than or equal to 50 nm, etchable by a solution of a specificchemical compound, and of a second dielectric material (3) of low heatconductivity not etchable by said solution; b) parallel trenches (T1,T2, T3, . . . , Ti . . . ) the lower limit of width (w) of whichcorresponds to the minimum linewidth of lithographic definition, spacedby at least 1 μm; c) parallel cavities (4 c) of retreat of the etchfront of the layers of said first dielectric material (2) by saidetching solution, along opposite surfaces of each trench; d) wirelikenanodimensioned residues of a conductor or semiconductor filler materialof said parallel nanocavities (4 c) constituting said parallel spacednanowires (4) organized in rows and columns; e) metallizations (5) onside surfaces of heat input/output of the septum, adapted toelectrically connect in parallel by groups said parallel nanowires (4);f) means (6) of electrical connection in series of said groups ofnanowires (4) in parallel, to two terminals of the whole series-parallelnetwork of nanowires (4) of the septum.
 16. The septum of claim 15,wherein said conductor or semiconductor material of high Seebeckcoefficient belongs to the group composed by an intrinsic or dopedsemiconductor, a metal, a metal alloy, an alloy of semimetals, an alloybetween a metal and a semimetal and mixtures thereof.
 17. The septum ofclaim 15, wherein said conductor or semiconductor material of highintrinsic Seebeck coefficient belongs to the groups composed ofmonocrystalline or polycrystalline silicon with natural isotopicpresence or enhanced presence of ²⁹Si, intrinsic or doped with donorand/or acceptor atoms, a silicon-germanium alloy with natural isotopicpresence or enhanced presence of ²⁹Si, either intrinsic or doped withdonor and/or acceptor atoms, tungsten, titanium and alloys thereof. 18.The septum of claim 15, wherein said first dielectric material (2) isSiO₂ and said second dielectric material (3) is Si₃N₄.
 19. The septum ofclaim 15, wherein said first dielectric material (2) is Si₃N₄ and saidsecond dielectric material (3) is SiO₂.
 20. The septum of claim 15,characterized in that the stack has a density of nanowires (4) ofaverage cross section of about 40 nm×20 nm, per unit of area of sidesurfaces of heat input/output of the stack up to 5×10¹⁰ nanowires/cm².21. The septum of claim 15, characterized in that the height (h) of thestack and periodicity or pitch of replication of said parallel trenches(T1, T2, T3, . . . , Ti . . . ) are of the same order of magnitude.